Research on High Thermal Conductivity Electronic Encapsulation Adhesive
With the rapid development of fields such as 5G communication and new energy vehicles, the power density of electronic devices is growing exponentially. Taking 5G micro base stations as an example, their power density can reach 3-5 times that of traditional base stations, and the core chip temperature exceeds 120 ℃ when operating at full load. Under this working condition, the sealing adhesive not only needs to have high thermal conductivity (>3 W/m · K), but also needs to solve the failure problems such as interface delamination and crack propagation caused by the coupling of thermal expansion and mechanical stress, which poses a dual challenge to the material system design.
The essence of thermal mechanical coupling failure lies in the interaction between the difference in coefficient of thermal expansion (CTE) of materials and temperature gradients:
CTE mismatch stress
Chip substrates (such as FR-4, CTE 12-16 ppm/℃) and conventional epoxy potting adhesives (CTE 60-80 ppm/℃) generate interfacial shear stress during temperature cycling. Finite element simulation shows that when Δ CTE>20 ppm/℃, the interface stress can reach 35 MPa, exceeding the bonding strength of most potting adhesives (<25 MPa).
Thermal resistance of thermal conduction path
Uneven distribution of fillers leads to a sharp increase in local thermal resistance, forming a "hot spot" (>150 ℃), triggering the material's glass transition (Tg), causing a 80% drop in modulus, and accelerating plastic deformation.
Fatigue accumulation effect
In high and low temperature cycles (-40 ℃) ↔ At 125 ℃, microcracks caused by CTE differences increase exponentially with the number of cycles, and the crack length can reach three times the initial value after 200 cycles (according to IPC-9701 standard)..
In response to the above issues, our company has achieved performance breakthroughs through multi-scale structural design:
Construction of gradient thermal conductivity network
Using a hybrid filler of boron nitride (in-plane thermal conductivity of 400 W/m · K) and aluminum oxide (low-cost), dense packing was achieved through particle size distribution (10 μ m+1 μ m), increasing the thermal conductivity to 3.8 W/m · K and reducing the CTE to 8 ppm/℃ (verified by DMA testing).
Interface stress buffer layer
Introducing polyurethane prepolymer to form a "soft hard" alternating structure, a 50-100 μ m flexible transition layer is generated at the chip interface, reducing the dispersion of interfacial shear stress by 42% (measured by digital image correlation DIC).
Fatigue resistant crosslinking system
By using a hybrid curing system of bismaleimide/epoxy, the Tg of the material was increased to 180 ℃, and the fluctuation range of storage modulus in high and low temperature cycles was narrowed to ± 15% (compared to ± 40% in traditional systems).
In the actual testing of a 5G micro base station module, the use of optimized sealing adhesive resulted in a 22 ℃ decrease in the peak temperature of the chip, and there was no interface delamination after 200 thermal cycles. With the popularization of third-generation semiconductors (GaN, SiC), future research needs to further synergize the electric thermal mechanical multi field coupling effect and develop next-generation material systems with CTE<5 ppm/℃ and thermal conductivity>5 W/m · K.
Contact
EMAIL : adayang@resinsealant.com
WhatsApp：+86-15910569196
Address :No. 5A, Zhongnan Hi-Tech, No. 588, Deng Yun Street, Tangxi Town, Jinhua City, Zhejiang Province, China
Do you have any questions? Please fill out the form